1. Field of the Invention
The present invention relates to a semiconductor device having a metal silicide layer capable of preventing the sheet resistance from increasing as a result of the thickness or the width of the electrode or the wire.
2. Description of the Related Art
Recently, since semiconductor devices are becoming smaller, a low resistance gate electrode having a polycide structure has been used in a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) type semiconductor devices. The polycide structure has a metal silicide layer formed on a polycrystalline silicon film. The gate electrode with the polycide structure can be obtained by successively forming a polycrystalline silicon film and a metal silicide layer on a gate oxide film.
A method of forming a gate electrode with a polycide structure will be explained hereinafter. FIGS. 1A to 1N are cross-sectional views showing a method of fabricating a conventional semiconductor device having a gate electrode of a polycide structure in process steps.
As shown in FIG. 1A, a silicon oxide film 2 is selectively formed at the surface of a silicon substrate 1 to define the element region. As shown in FIG. 1B, a gate oxide film 3 is formed on the element region. As shown in FIG. 1C, a polycrystalline silicon film 4 is formed on the silicon oxide film 2 and the gate oxide film 3 by, for example, the CVD (chemical vapor deposition) method.
As shown in FIG. 1D, a large amount of phosphorus is doped into the polycrystalline silicon film 4 by applying a heat treatment to the polycrystalline silicon film 4 in an oxidizing atmosphere containing POCl.sub.3. Accordingly, a phosphorus glass layer 5 is generated on the surface of the polycrystalline silicon film 4. As shown in FIG. 1E, the phosphorus glass layer 5 is eliminated by wet etching. The step of forming the polycrystalline silicon film 4 shown in FIG. 1C and the step of doping phosphorus to the polycrystalline silicon film 4 shown in FIG. 1D can be performed at the same time.
Then, as shown in FIG. 1F, a metal silicide thin film 7 is formed on the polycrystalline silicon film 4 by the PVD (physical vapor deposition) method or the CVD method. As shown in FIG. 1G, a silicon layer 8 is formed on the metal silicide thin film 7 by the PVD method or the CVD method. As shown in FIG. 1H, the polycrystalline silicon film 4, the metal silicide thin film 7 and the silicon layer 8 are patterned by dry etching after performing ordinary resist application step, and exposing and developing step. Accordingly, a gate electrode with a polycide structure can be formed.
As shown in FIG. 1I, as needed, by injecting impurity ions in the surface of the element region, an LDD (lightly doped drain) layer 9 is formed. As shown in FIG. 1J, an oxide film 10 is formed with good step coverage on the entire surface. As shown in FIG. 1K, a side wall insulating film 10a of the oxide film can be obtained by remaining the oxide film 10 only on the side wall surface of the polycrystalline silicon film 4, the metal silicide thin film 7 and the silicon layer 8 by anisotropic etching.
Then, as shown in FIG. 1L, impurity ions are injected in the surface of the element region to form a source-drain diffusion layer 11. As shown in FIG. 1M, an interlayer insulating film 12 is deposited on the entire surface. As shown in FIG. 1N, after selectively forming contact holes 12a in the interlayer insulating film 12, the contact holes 12a are buried with a conductive film. Therefore, drawing electrodes 13 can be formed.
In the gate electrode obtained by the above-mentioned steps, if the metal silicide thin film 7 is formed on the uppermost layer of the electrode, the metal silicide thin film 7 is damaged by ions, when the oxide film 10 is selectively eliminated by the anisotropic etching. The metal silicide thin film 7 may also be peeled off by the abnormal oxidation at the time of heat treatment under the oxidizing atmosphere. Therefore, in order to prevent the peel-off of the metal silicide thin film 7, the silicon layer 8 is formed on the metal silicide thin film 7. A method of forming a polycrystalline silicon film or an amorphous protection film on a refractory metal silicide layer is disclosed in Japanese Patent Application Laid-Open No. 1-205468. The method can prevent the damage on the refractory metal silicide layer in the step of forming the side wall insulating film 10a of the gate electrode. Also, the method can maintain the adherence between the polycrystalline silicon film and the refractory metal silicide layer in the subsequent heat treatment step.
Further, with the silicon layer 8 formed on the refractory metal silicide thin film 7, since the surface of both diffusion layer 11 and the gate electrode that is the final point of the dry etching are made of silicon when the contact holes to reach the diffusion layer 11 and the gate electrode are provided in the interlayer insulating film 12 after forming the interlayer insulating film 12, it is advantageous in that a margin with respect to the dry etching can be wider.
Further, in cleaning the contact holes 12a after etching, a cleaning liquid produced only for a silicon film can be used. Moreover, since the drawing electrodes are to be connected only to a silicon film, a process margin for obtaining a low resistance contact can be wider as well.
Furthermore, since the silicon layer 8 as the uppermost layer has a reflectance lower than that of the refractory metal silicide thin film 7, it is advantageous in that a resist film can be exposed with a good shape at the time of patterning the polycrystalline silicon film 4, the metal silicide thin film 7 and the silicon layer 8.
However, the conventional semiconductor device obtained by the fabricating method shown in FIGS. 1A to 1N has the below-mentioned problems. That is, semiconductor devices are designed to be smaller not only in the direction parallel to the substrate surface (horizontal direction) but also in the substrate thickness direction (vertical direction) according to the recent movement toward a smaller size and high integration. However, according to the above-mentioned conventional technology, if the refractory metal silicide layer such as a titanium silicide film is formed with a thickness of 200 nm or less, a problem is involved in that the sheet resistance is increased whenever a heat treatment at 800.degree. C. or higher is performed the silicide film.
FIG. 2 is a graph showing the relationship between the sheet resistance and the wire width, with the sheet resistance along the vertical axis and the wire width along the horizontal axis. FIG. 2 shows the sheet resistance of a wire having a laminated structure consisting a 100 nm thickness polycrystalline silicon film doped with phosphorus, a 100 nm thickness titanium silicide film (refractory metal silicide layer) and a 50 nm thickness silicon layer applied with a heat treatment at 850.degree. C. for 30 minutes. As shown in FIG. 2, the finer the wire width becomes from 0.5 .mu.m, the resistance of the wire becomes larger to have a larger variance in the sheet resistance in the same wafer.
Accordingly, the conventional semiconductor device has a problem in that the sheet resistance increase caused by the heat treatment becomes conspicuous as the electrode width or the wire width becomes finer, or the silicide layer becomes thinner.
Various kinds of semiconductor devices having a gate electrode with a polycide structure having excellent acid resistance, etching resistance and heat resistance have been proposed. For example, a semiconductor device having a gate electrode with a laminated structure is disclosed in Japanese Patent Application Laid-Open No. 2-35773. The gate electrode has a barrier metal layer made of titanium nitride or titanium carbonate formed on a silicide layer, and an acid resistant silicide layer made of molybdenum silicide, tungsten silicide or tantalum silicide formed on the barrier metal layer. Further, a semiconductor device having a gate electrode with a laminated structure where a polycrystalline silicon layer and a refractory metal layer or a refractory metal silicide layer is formed on a substrate is disclosed in Japanese Patent Application Laid-Open No. 62-86865.
However, since the gate electrodes of the conventional laminated structures are not provided with a silicon layer as the uppermost layer, in forming contact holes to reach a diffusion layer and a gate electrode in an interlayer insulating film after the formation of the interlayer insulating film, a dry etching condition needs to be selected in order to have a larger selective ratio between the material of the interlayer insulating film, and the material of the diffusion layer and the uppermost layer of the gate electrode.
Besides, a cleaning liquid not causing damage to either of the material of the uppermost layer of the electrode or silicon needs to be selected at the time of cleaning the contact holes after etching. Accordingly, with the semiconductor devices disclosed in Japanese Patent Application Laid Open Nos. 2-35773 and 62-86865, it is difficult to have a good contact of electric characteristics to both gate electrode and diffusion layer.